Fabrication

Game-Changing System Performance

Ultra-Wide Bandwidth
Ultra-Low Loss

Quilt Packaging can be implemented at the foundry or OSAT

In order to get the full benefit from Quilt Packaging, chips and packaging are designed with QP in mind from the beginning. QP can be implemented in a variety of substrates, including Si, GaAs, InP, SiGe, SiC, GaN, and more. Wafer fabrication on the front end is exactly like that of any other process, and QP is implemented during the Back-End-of-Line processing.

Quilt Packaging
Fabrication Process

Finish Front-End-Of-Line
The Quilt Packaging fabrication process begins as the front end work finishes, very similar to a “via-middle” approach for fabricating TSVs. Quilt Packaging can occur at the foundry or at an assembly house capable of the etching, metallization, and other Back-End-of-Line process (just like via-middle).
Nodule Definition Etch, Metallization & CMP
An etch mask is used to define the nodule features, and the “mold” for nodules is created by removing material through an etch process. Following nodule definition etch, the wafer undergoes seed layer deposition, electropating build-up of the nodule metal, and CMP removal of the overburden.
Finish Global Chip Interconnects
After the CMP step, the wafer now has metal nodules “embedded” in what would usually be the dicing streets and the wafer looks otherwise as it did prior to nodule definition etch. At this point the rest of the back end of line is completed, with signal connections made across the chip and to nodules as needed.‚Äč
Singulate QP Die, Assemble & Reflow
Once global interconnects are made, a final separation etch mask is used to protect the die surface during the separation step. Wafer singulation is implemented by dry etching or a combination of dry etching and grinding or sawing. Chips are then assembled into “Quilts” and reflowed to form one large “Metachip.” This quilt is then treated as if it were one large chip, and ends up in a package, on a board, on ceramic, etc.

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